Research
Research Interests#
- Quantum Computer Architecture
- Quantum Error Correction
- Machine Learning
International Conference Proceedings#
- Shota Ikari, Yuga Hirai, Yosuke Ueno, Yasunari Suzuki, and Hiroshi Nakamura, “Circuit-Level Implementation and Evaluation of Logical SH Gates in the Surface Code,” In Proceedings of the IEEE International Conference on Quantum Computing and Engineering (QCE), 2026. (To appear) (QCE 2026 poster)
Preprints#
- Shota Ikari, Yuga Hirai, Yasunari Suzuki, Hiroshi Nakamura, Yosuke Ueno", Do Not Let CNOTs Overwhelm the Decoder: Scheduling Transversal Gates for Fast FTQC," arXiv:2608.11719 [quant-ph], 2026.
- Yuga Hirai, Shota Ikari, Yosuke Ueno, Yasunari Suzuki, “No More Hooks in the Surface Code: Distance-Preserving Syndrome Extraction for Arbitrary Layouts at Minimum Depth,” arXiv:2603.01628 [quant-ph], 2026.
- Yuga Hirai, Shota Ikari, Yosuke Ueno, Yasunari Suzuki, “A 2d x d x d Spacetime Volume Implementation of a Logical S Gate in the Surface Code,” arXiv:2604.13632 [quant-ph], 2026.
Talks and Posters#
- Yuga Hirai, Shota Ikari, Yosuke Ueno, and Yasunari Suzuki, “No More Hooks in the Surface Code: Distance-Preserving Syndrome Extraction for Arbitrary Layouts at Minimum Depth,” 8th International Conference on Quantum Error Correction, 2026. (QEC 2026 poster) [arXiv]
- Yuga Hirai, Shota Ikari, Yosuke Ueno, and Yasunari Suzuki, “A 2d x d x d Spacetime Volume Implementation of a Logical S Gate in the Surface Code,” 5th Quantum Computing Theory in Practice Conference, 2026. (QCTiP 2026 poster) [arXiv]
Awards#
| Date | Name |
|---|---|
| 2025.06 | 2nd place, Agile-X FPGA AI Design Hackathon |
Scholarships#
| Period | Name |
|---|---|
| 2023.04 - 2025.03 | Kyoto University CF Project Scholarship |
