研究

研究関心

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• 量子計算機アーキテクチャ
• 量子誤り訂正
• 機械学習

International Conference Proceedings

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1. Shota Ikari, Yuga Hirai, Yosuke Ueno, Yasunari Suzuki, Hiroshi Nakamura, “Circuit-Level Implementation and Evaluation of Logical SH Gates in the Surface Code,” In Proceedings of the IEEE International Conference on Quantum Computing and Engineering (QCE), 2026. (To appear) (QCE 2026 poster)

Preprints

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1. Shota Ikari, Yuga Hirai, Yasunari Suzuki, Hiroshi Nakamura, Yosuke Ueno", Do Not Let CNOTs Overwhelm the Decoder: Scheduling Transversal Gates for Fast FTQC," arXiv:2608.11719 [quant-ph], 2026.
2. Yuga Hirai, Shota Ikari, Yosuke Ueno, Yasunari Suzuki, “No More Hooks in the Surface Code: Distance-Preserving Syndrome Extraction for Arbitrary Layouts at Minimum Depth,” arXiv:2603.01628 [quant-ph], 2026.
3. Yuga Hirai, Shota Ikari, Yosuke Ueno, Yasunari Suzuki, “A 2d x d x d Spacetime Volume Implementation of a Logical S Gate in the Surface Code,” arXiv:2604.13632 [quant-ph], 2026.

Talks and Posters

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1. Yuga Hirai, Shota Ikari, Yosuke Ueno, Yasunari Suzuki, “No More Hooks in the Surface Code: Distance-Preserving Syndrome Extraction for Arbitrary Layouts at Minimum Depth,” 8th International Conference on Quantum Error Correction, 2026. (QEC 2026 poster) [arXiv]
2. Yuga Hirai, Shota Ikari, Yosuke Ueno, Yasunari Suzuki, “A 2d x d x d Spacetime Volume Implementation of a Logical S Gate in the Surface Code,” 5th Quantum Computing Theory in Practice Conference, 2026. (QCTiP 2026 poster) [arXiv]
3. 猪狩 翔太, 平井 優我, 上野 洋典, 鈴木 泰成, 山本 直樹, 中村 宏, 「表面符号上の Transversal CNOT ゲートを対象とした window decoder の検討」, 第203回HPC・第17回QS合同研究発表会, 北海道, 2026年3月. 口頭発表.
4. 猪狩 翔太, 伊藤 向子, 「FPGAを用いたYOLOv5nのアクセラレーション - Hackathonを通じた実装報告 -」, リコンフィギャラブルシステム研究会 (RECONF), 2025年9月. 招待講演.

Awards

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Scholarships

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